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This is a test suit spacewire using a model on systemC with a verilog with graphical interface - Latin American Group Integrated Circuits Development Open Source - GLADICOS


GitHub		https://github.com/GLADICOS/SPACEWIRESYSTEMC
Size		666.5M (666.4M (+28K))
Commits		182 (181 (+1))
Update Stats		0s ... 4m19s [Ø (last 10) 1s (1,1,1,2,1,1,1,1,2,1))]
Last Change		2022-09-28 18:57:05
Last Check		2025-11-03 18:46:44
Created		2020-06-15 06:50:57

Messages as of last check on 2025-11-03 18:46:44

Operation

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