| SCR1 is a high-quality open-source RISC-V MCU core in Verilog - Syntacore - syntacore |
 GitHub |
https://github.com/syntacore/scr1 | |
| Size | 6.3M (6.2M (+56K)) | |
| Commits | 69 (68 (+1)) | |
| Update Stats | 1s ... 3s [Ø (last 10) 2s (2,2,2,2,2,1,1,1,1,1))] | |
| Last Change | 2024-11-15 17:17:00 | |
| Last Check | 2025-11-25 18:48:12 | |
| Created | 2023-09-17 17:10:21 |
Operation
Mirror (Self)Verifying url ...Mail to Andreas Kupries