Store 3585

SPI Verilog Master & Slave modules - FreeCores - freecores
GitHub GitHub https://github.com/freecores/spiverilogmaster_slave
Size 168K (164K (+4K))
Commits 1 (0 (+1))
Update Stats 0s ... 6s [Ø (last 10) 1s (1,1,1,1,1,1,1,1,2,1))]
Last Change 2023-09-17 10:26:38
Last Check 2025-06-30 01:16:38
Created 2023-09-17 10:26:38

Messages as of last check on 2025-06-30 01:16:38

Operation

Verifying url ...

Contact information

Mail to Andreas Kupries