A tool that converts SystemVerilog to Verilog. Use Design Compiler, so it is 100% compatible. - Bespoke Silicon Group - bespoke-silicon-group |
GitHub | https://github.com/bespoke-silicon-group/bsg_sv2v | |
Size | 296K (288K (+8K)) | |
Commits | 53 (52 (+1)) | |
Update Stats | 1s ... 13s [Ø (last 10) 1s (1,1,1,1,1,2,1,1,1,1))] | |
Last Change | 2023-05-12 18:57:07 | |
Last Check | 2023-09-15 18:36:35 | |
Created | 2022-07-24 10:10:47 |
Operation
Verifying url ...
Mail to Andreas Kupries