RiSC 16 is a simple 16 bit instruction set with 8 instructions and 3 instruction formats. This is an RTL implementation in verilog, instruction set simulator and a random instruction generator in system verilog and a rudimetary assembler in python - Ashwin Rajesh - Ashwin-Rajesh

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GitHub GitHub 0 https://github.com/Ashwin-Rajesh/RiSC-16

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