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An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more - UC Berkeley Architecture Research - ucb-bar


GitHub		https://github.com/ucb-bar/chipyard
Size		27.1M (27.1M (+4K))
Commits		4861 (4860 (+1))
Update Stats		0s ... 9s [Ø (last 10) 3s (3,3,3,3,3,3,3,2,2,2))]
Last Change		2023-09-12 03:57:04
Last Check		2023-09-16 03:47:28
Created		2023-03-30 00:01:28

Messages as of last check on 2023-09-16 03:47:28

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