Pending submissions: 17
| When | Url | VCS | Name |
|---|---|---|---|
| 2024-04-28 19:35:12 | https://github.com/rejunity/z80-open-silicon |
github
|
Z80 open-source silicon. Goal is to become a silicon proven, pin compatible, open-source replacement for classic Z80. - Renaldas Zioma - rejunity |
| 2024-04-28 19:35:06 | https://github.com/hutch31/Balsa-AES-Core |
github
|
Asynchronous AES core written using the Balsa hardware description language - Guy Hutchison - hutch31 |
| 2024-04-28 19:34:23 | https://github.com/hutch31/tv80 |
github
|
TV80 Z80-compatible microprocessor - Guy Hutchison - hutch31 |
| 2024-04-28 19:33:54 | https://github.com/gdevic/A-Z80 |
github
|
An implementation of the Z80 CPU for Altera, Xilinx and Lattice FPGAs - Goran Devic - gdevic |
| 2024-04-28 19:33:35 | https://github.com/gdevic/Z80Explorer |
github
|
Visual Zilog Z-80 netlist-level simulator - Goran Devic - gdevic |
| 2024-04-28 19:33:16 | https://github.com/abnoname/iceZ0mb1e |
github
|
FPGA 8-Bit TV80 SoC for Lattice iCE40 with complete open-source toolchain flow using yosys and SDCC - abnoname |
| 2024-04-28 19:32:40 | https://github.com/Obijuan/Z80-FPGA |
github
|
Z80 CPU for OpenFPGAs, with Icestudio - Juan Gonzalez-Gomez - Obijuan |
| 2024-04-27 16:13:56 | https://github.com/grayresearch/lcc-xr16 |
github
|
The lcc retargetable ANSI C compiler, including code generation for the xr16 instruction set architecture - Jan Gray - grayresearch |
| 2024-04-27 15:24:33 | https://github.com/grayresearch/caravel_s3ga |
github
|
S3GA serial FPGA + efabless Caravel project - Jan Gray - grayresearch |
| 2024-04-27 15:24:09 | https://github.com/grayresearch/xsoc-xr16 |
github
|
Snapshot of the April 2000 XSOC/xr16 Project Beta 0.93, collateral for Jan Gray's series \"Building a RISC System in an FPGA\" published in Feb, Mar, Apr 2000 Circuit Cellar magazine - Jan Gray - grayresearch |
| 2024-04-27 14:17:18 | https://github.com/grayresearch/s3ga |
github
|
S3GA: a simple scalable serial FPGA - Jan Gray - grayresearch |
| 2024-04-27 14:16:43 | https://github.com/TinyTapeout/tt02-verilog-demo |
github
|
Verilog demo for TT02 - Tiny Tapeout - TinyTapeout |
| 2024-04-27 14:15:04 | https://github.com/grayresearch/tt02-s4ga |
github
|
TinyTapeout2 Super Slow Serial SRAM FPGA - Jan Gray - grayresearch |
| 2024-04-27 14:12:33 | https://github.com/grayresearch/s4ga |
github
|
a small simple slow serial FPGA core - Jan Gray - grayresearch |
| 2024-04-27 14:10:34 | https://github.com/grayresearch/cx |
github
|
Proposed RISC-V Composable Custom Extensions Specification - Jan Gray - grayresearch |
| 2024-04-27 13:58:35 | https://github.com/riscv-admin/sig-soft-cpu/ |
github
|
Group administration repository for SIG: SoftCPU - RISC-V Administrative Materials - riscv-admin |
| 2024-02-08 18:29:15 | https://github.com/Open-Lab-Starter-Kit/OLSK-Large-3D-Printer |
github
|
Open Source 3D Printer - Large version - Open Lab Starter Kit - Open Lab Starter Kit - Open-Lab-Starter-Kit |
Mirror (Self)