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4 stage, in-order, secure RISC-V core based on the CV32E40P with Zfinx and Zce ISA extentions - OpenHW Group - openhwgroup


GitHub		https://github.com/openhwgroup/cv32e41p
Size		6.2M (6.2M (+4K))
Commits		1744 (0 (+1744))
Update Stats		0s ... 15s [Ø (last 10) 1s (1,1,1,2,1,1,1,1,1,1))]
Last Change		2024-02-17 18:26:40
Last Check		2025-09-12 13:30:17
Created		2024-02-17 18:26:40

Messages as of last check on 2025-09-12 13:30:17

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