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CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals. - OpenHW Group - openhwgroup


GitHub		https://github.com/openhwgroup/cvw
Size		61.3M (60.9M (+364K))
Commits		19403 (19388 (+15))
Update Stats		2s ... 14s [Ø (last 10) 8s (8,7,7,7,7,7,8,8,8,8))]
Last Change		2026-01-08 01:47:23
Last Check		2026-01-08 01:46:58
Created		2024-02-17 18:25:42

Messages as of last check on 2026-01-08 01:46:58

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