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CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals. - OpenHW Group - openhwgroup


GitHub		https://github.com/openhwgroup/cvw
Size		63.2M (63.1M (+84K))
Commits		19548 (19542 (+6))
Update Stats		2s ... 20s [Ø (last 10) 10s (9,9,8,9,9,8,8,20,10,10))]
Last Change		2026-02-27 12:27:22
Last Check		2026-02-27 12:27:01
Created		2024-02-17 18:25:42

Messages as of last check on 2026-02-27 12:27:01

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