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CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals. - OpenHW Group - openhwgroup


GitHub		https://github.com/openhwgroup/cvw
Size		63.7M (63.7M (+16K))
Commits		19570 (19569 (+1))
Update Stats		2s ... 20s [Ø (last 10) 11s (8,20,10,10,10,10,10,10,11,10))]
Last Change		2026-03-19 13:37:09
Last Check		2026-03-19 13:36:46
Created		2024-02-17 18:25:42

Messages as of last check on 2026-03-19 13:36:46

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