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CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals. - OpenHW Group - openhwgroup


GitHub		https://github.com/openhwgroup/cvw
Size		55.3M (55.3M (+16K))
Commits		19063 (19061 (+2))
Update Stats		2s ... 14s [Ø (last 10) 4s (4,4,4,4,4,4,4,4,5,5))]
Last Change		2025-07-01 05:36:48
Last Check		2025-07-01 05:36:38
Created		2024-02-17 18:25:42

Messages as of last check on 2025-07-01 05:36:38

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