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CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals. - OpenHW Group - openhwgroup


GitHub		https://github.com/openhwgroup/cvw
Size		59.8M (58.0M (+1.9M))
Commits		19265 (19243 (+22))
Update Stats		2s ... 14s [Ø (last 10) 6s (6,6,5,6,6,7,7,8,7,7))]
Last Change		2025-10-30 04:57:05
Last Check		2025-10-30 04:56:41
Created		2024-02-17 18:25:42

Messages as of last check on 2025-10-30 04:56:41

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