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A FPGA friendly 32 bit RISC-V CPU implementation - SpinalHDL - SpinalHDL


GitHub		https://github.com/SpinalHDL/VexRiscv/
Size		18.5M (18.3M (+212K))
Commits		1704 (1697 (+7))
Update Stats		1s ... 5s [Ø (last 10) 3s (3,3,3,3,3,3,3,3,3,3))]
Last Change		2025-12-25 07:36:36
Last Check		2026-01-07 21:56:41
Created		2023-10-21 18:06:42

Messages as of last check on 2026-01-07 21:56:41

Operation

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