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A FPGA friendly 32 bit RISC-V CPU implementation - SpinalHDL - SpinalHDL


GitHub		https://github.com/SpinalHDL/VexRiscv/
Size		18.3M (18.2M (+36K))
Commits		1697 (1695 (+2))
Update Stats		1s ... 5s [Ø (last 10) 3s (3,3,2,3,3,4,3,3,3,3))]
Last Change		2025-10-23 14:37:15
Last Check		2025-10-30 01:56:44
Created		2023-10-21 18:06:42

Messages as of last check on 2025-10-30 01:56:44

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