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A FPGA friendly 32 bit RISC-V CPU implementation - SpinalHDL - SpinalHDL


GitHub		https://github.com/SpinalHDL/VexRiscv/
Size		18.6M (18.5M (+156K))
Commits		1709 (1704 (+5))
Update Stats		1s ... 8s [Ø (last 10) 4s (4,4,3,4,3,5,3,3,3,8))]
Last Change		2026-02-14 00:57:13
Last Check		2026-02-27 09:26:43
Created		2023-10-21 18:06:42

Messages as of last check on 2026-02-27 09:26:43

Operation

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