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A FPGA friendly 32 bit RISC-V CPU implementation - SpinalHDL - SpinalHDL


GitHub		https://github.com/SpinalHDL/VexRiscv
Size		18.4M (18.4M (+36K))
Commits		1697 (1695 (+2))
Update Stats		0s ... 5s [Ø (last 10) 4s (3,4,4,3,3,4,4,4,4,4))]
Last Change		2025-10-23 14:06:45
Last Check		2025-10-30 01:26:39
Created		2023-09-17 17:10:12

Messages as of last check on 2025-10-30 01:26:39

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