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A FPGA friendly 32 bit RISC-V CPU implementation - SpinalHDL - SpinalHDL


GitHub		https://github.com/SpinalHDL/VexRiscv
Size		18.3M (18.3M (+44K))
Commits		1692 (1691 (+1))
Update Stats		0s ... 5s [Ø (last 10) 3s (3,3,4,3,4,3,3,3,3,3))]
Last Change		2025-06-09 08:56:59
Last Check		2025-07-01 01:56:39
Created		2023-09-17 17:10:12

Messages as of last check on 2025-07-01 01:56:39

Operation

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