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A FPGA friendly 32 bit RISC-V CPU implementation - SpinalHDL - SpinalHDL


GitHub		https://github.com/SpinalHDL/VexRiscv
Size		18.8M (18.6M (+156K))
Commits		1709 (1704 (+5))
Update Stats		0s ... 6s [Ø (last 10) 4s (4,4,4,4,4,6,4,4,5,5))]
Last Change		2026-02-13 23:36:02
Last Check		2026-02-27 08:46:43
Created		2023-09-17 17:10:12

Messages as of last check on 2026-02-27 08:46:43

Operation

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