| DDR2 mem controller for Digilent Genesys Board - FreeCores - freecores | 
| https://github.com/freecores/genesys_ddr2 | ||
| Size | 692K (688K (+4K)) | |
| Commits | 3 (0 (+3)) | |
| Update Stats | 0s ... 2s [Ø (last 10) 1s (1,1,1,1,1,1,1,1,1,1))] | |
| Last Change | 2023-09-17 10:31:04 | |
| Last Check | 2025-10-29 00:56:48 | |
| Created | 2023-09-17 10:31:04 | 
Operation
Verifying url ...
Mail to Andreas Kupries