DiseƱo digital con FPGAs libres, en lenguaje Verilog y con la placa IceZUM Alhambra - FPGAwars - FPGAwars |
https://github.com/FPGAwars/Tutorial-verilog-openfpga-icezum | ||
Size | 7.1M (7.1M (+4K)) | |
Commits | 8 (0 (+8)) | |
Update Stats | 0s ... 1m12s [Ø (last 10) 1s (1,1,1,1,1,1,2,1,1,1))] | |
Last Change | 2023-09-17 09:46:26 | |
Last Check | 2025-06-29 18:26:40 | |
Created | 2023-09-17 09:46:26 |
Operation
Verifying url ...
Mail to Andreas Kupries