| Verilator open-source SystemVerilog simulator and lint system - CHIPS Alliance - chipsalliance |
| https://github.com/chipsalliance/verilator | ||
| Size | 95.1M (93.9M (+1.2M)) | |
| Commits | 8789 (8779 (+10)) | |
| Update Stats | 0s ... 21s [Ø (last 10) 4s (3,4,4,3,3,4,4,4,4,4))] | |
| Last Change | 2025-11-27 13:26:53 | |
| Last Check | 2025-11-27 13:26:50 | |
| Created | 2023-06-01 00:01:21 |
Operation
Verifying url ...
Mail to Andreas Kupries