| Verilator open-source SystemVerilog simulator and lint system - CHIPS Alliance - chipsalliance |
| https://github.com/chipsalliance/verilator | ||
| Size | 135.1M (133.7M (+1.4M)) | |
| Commits | 9314 (9302 (+12)) | |
| Update Stats | 0s ... 21s [Ø (last 10) 7s (6,7,6,8,7,7,6,7,8,9))] | |
| Last Change | 2026-03-17 20:17:54 | |
| Last Check | 2026-03-17 20:17:01 | |
| Created | 2023-06-01 00:01:21 |
Operation
Verifying url ...
Mail to Andreas Kupries