| Verilator open-source SystemVerilog simulator and lint system - CHIPS Alliance - chipsalliance |
 GitHub |
https://github.com/chipsalliance/verilator | |
| Size | 83.3M (82.2M (+1.1M)) | |
| Commits | 8640 (8617 (+23)) | |
| Update Stats | 0s ... 21s [Ø (last 10) 7s (9,11,10,10,10,11,2,4,3,4))] | |
| Last Change | 2025-10-28 13:56:45 | |
| Last Check | 2025-10-28 13:56:42 | |
| Created | 2023-06-01 00:01:21 |
Operation
Mirror (Self)Verifying url ...Mail to Andreas Kupries