| An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more - UC Berkeley Architecture Research - ucb-bar |
| https://github.com/ucb-bar/chipyard | ||
| Size | 78.2M (78.2M (+4K)) | |
| Commits | 7366 (7360 (+6)) | |
| Update Stats | 0s ... 13s [Ø (last 10) 7s (7,8,8,6,6,8,8,7,8,7))] | |
| Last Change | 2026-01-29 13:07:11 | |
| Last Check | 2026-02-01 20:37:03 | |
| Created | 2023-03-30 00:01:28 |
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