| An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more - UC Berkeley Architecture Research - ucb-bar |
| https://github.com/ucb-bar/chipyard | ||
| Size | 78.1M (78.1M (+12K)) | |
| Commits | 7358 (7357 (+1)) | |
| Update Stats | 0s ... 13s [Ø (last 10) 7s (7,6,9,7,6,7,7,7,8,8))] | |
| Last Change | 2026-01-09 15:46:35 | |
| Last Check | 2026-01-09 15:46:01 | |
| Created | 2023-03-30 00:01:28 |
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