| An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more - UC Berkeley Architecture Research - ucb-bar |
| https://github.com/ucb-bar/chipyard | ||
| Size | 78.6M (78.6M (+36K)) | |
| Commits | 7393 (7390 (+3)) | |
| Update Stats | 0s ... 13s [Ø (last 10) 8s (8,10,7,8,8,8,9,7,8,8))] | |
| Last Change | 2026-03-27 21:57:06 | |
| Last Check | 2026-03-27 21:56:42 | |
| Created | 2023-03-30 00:01:28 |
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