Basic USB-CDC device core (Verilog) - ultraembedded |
GitHub | https://github.com/ultraembedded/coreusbcdc | |
Size | 588K (584K (+4K)) | |
Commits | 10 (0 (+10)) | |
Update Stats | 0s ... 12s [Ø (last 10) 1s (1,1,1,1,1,1,1,1,1,1))] | |
Last Change | 2022-07-24 10:34:14 | |
Last Check | 2023-09-15 12:56:37 | |
Created | 2022-07-24 10:34:14 |
Operation
Verifying url ...
Mail to Andreas Kupries