| Basic USB-CDC device core (Verilog) - ultraembedded |
| https://github.com/ultraembedded/coreusbcdc | ||
| Size | 588K (584K (+4K)) | |
| Commits | 10 (0 (+10)) | |
| Update Stats | 0s ... 12s [Ø (last 10) 1s (1,0,1,1,1,1,1,1,1,1))] | |
| Last Change | 2022-07-24 10:34:14 | |
| Last Check | 2025-10-27 21:36:39 | |
| Created | 2022-07-24 10:34:14 |
Operation
Verifying url ...
Mail to Andreas Kupries